1. Field of the Invention
This invention relates to computer systems and, more particularly, to apparatus for transferring data from a memory array of a frame buffer to a shift register used to provide data to an output display device.
2. History of the Prior Art
One of the significant problems involved in increasing the operational speed of desktop computers has been in finding ways to increase the rate at which information is transferred to an output display device. Many of the various forms of data presentation which are presently available require that copious amounts of data be transferred. For example, if a computer output display monitor is operating in a color mode in which 1024.times.780 pixels are displayed on the screen at once and the mode is one in which thirty-two bits are used to define each pixel, then a total of over twenty-five millions bits of information must be transferred to the screen with each individual picture (called a "frame") that is displayed. Typically, sixty frames are displayed each second so that over one and one-half billion bits must be transferred each second in such a system. This requires a very substantial mount of processing power.
In order to provide such a large amount of information to an output display device, computer systems typically utilize a frame buffer which holds the pixel data which is to be displayed on the output display.
Typically a frame buffer offers a sufficient amount of dynamic random access memory (DRAM) to store one frame of data to be displayed. The information in the frame buffer is transferred to the display from the frame buffer sixty or more times each second. After (or during) each transfer, the pixel data in the frame buffer is updated with the new information to be displayed in the next frame. Prior art frame buffers capable of holding the necessary amount of information are quite large and complicated.
In fact, a number of operations which might help to increase the speed of operation of a frame buffer and the transfer of the data in the frame buffer to the output display device are not implemented because the mount of circuitry required is too extensive and too complicated to be economic.
For example, transferring the data to and from the frame buffer is very slow because of the manner in which the frame buffers are constructed. Various improvements have been made to speed access in frame buffers. For example, two-ported video random access memory (VRAM) has been substituted for dynamic random access memory so that information may be transferred from the frame buffer to the display at the same time other information is being loaded into the frame buffer.
One of the problems which all frame buffers have faced is caused by the method by which data is transferred from the frame buffer to an output display device. Typically, the display device is a cathode ray tube which renders the pixel data stored in the frame buffer on a screen in a series of rows. A typical display is comprised of 780 horizontal rows, each of which includes as many as 1024 individual pixels. A frame is described on the display by writing individual rows of pixels starting at the upper left corner of the display. Each row of pixels is rendered from left to right across the display before a next row in sequence is begun, When a row is completed, the next row below is begun at the left side of the screen. Each row is rendered in order until the last row at the bottom of the screen is completed. This completes one frame. Then the process starts over from the beginning with the next frame at the upper left corner of the display. As explained above, in the typical display sixty individual frames are presented each second.
In order to cause each of the pixels stored in the frame buffer to be presented at the appropriate position on the display, it is necessary to read the data for each pixel and transfer that data to the circuitry which controls its rendering on the output display device. In a typical VRAM, the pixel data to be displayed is read a row at a time and placed in a shift register at the output of the frame buffer. This is accomplished by providing one stage of shift register memory for each column of the array and writing into the shift register in response to a row selection accomplished by the row decode signal. The data stored at each cell of the row is amplified by a bitline sense amplifier for that column and transferred to the associated shift register stage. The data is then available in the shift register so that it may be shifted to the display a pixel at a time in order to fit the above-described sequence in which the pixels of a frame are displayed on a display device.
Such a prior art shift register stores an entire row of pixel data stored in the array of the frame buffer. Such a shift register size has always been necessary because of the architectural arrangement by which a stage of the output shift register is associated with each column of the array. However, to hold this mount of data such a shift register must be capable of holding the number of pixels in a row multiplied by the largest number of bits in a pixel. For thirty-two bit color displays having a size of 512.times.512 pixels, this requires a shift register capable of holding 512.times.32 or a total of over sixteen thousand bits. A shift register capable of storing this amount of data and the attendant circuitry for transferring the data from the frame buffer array to the shift register require a very substantial amount of die space. Moreover, the pixel data stored by such a shift register must further amplified before it is furnished to the display control circuitry because the bitline sense amplifiers do not provide a sufficient amount of amplification. This addition amplification slows the operation of writing to the display.
It has now been determined that such a large shift register is unnecessary for providing sufficient data to keep up with the display of pixel data on an output display device. It is therefore desirable to provide an architecture which allows the size of the shift register to be reduced in order to reduce the complexity and expense of frame buffer circuitry. It is also desirable to provide a more rational arrangement of circuit architecture for transferring data from a frame buffer array to a shift register used for furnishing pixel data to an output display device.